PACT XPP Schweiz AG v. Intel — Federal Circuit Affirms Noninfringement on Forfeited Argument and Prosecution Estoppel

Background

PACT XPP Schweiz AG, a Swiss patent licensing entity, owned two patents on computer processor architecture. U.S. Patent 8,312,301 (the ‘301 patent) covers a processor that can selectively change the operating clock frequencies of its constituent elements; its key representative claim requires “a plurality of data processing elements adapted for programmably processing sequences.” U.S. Patent 8,471,593 (the ‘593 patent) covers a multi-core processor design in which some cores have a “physically dedicated connection” to a specific assigned memory unit.

PACT sued Intel Corporation in the District of Delaware, alleging that Intel’s multiprocessor computing systems infringed claims of both patents. The district court granted summary judgment of noninfringement on both patents. PACT appealed to the Federal Circuit — the companies’ second Federal Circuit encounter in this patent family after Intel v. PACT XPP Schweiz (Fed. Cir. 2023, No. 22-1037) addressed related patents.

The Court’s Holding

The Federal Circuit affirmed on both patents, for distinct reasons on each.

The ‘301 patent — forfeited capability theory. The district court construed the word “sequences” to require sequences of data, based on arguments PACT itself made during a parallel inter partes review (IPR) proceeding before the Patent Office. Under that construction, there was no dispute that Intel’s accused processors handle sequences of instructions — not data — so there was no literal infringement. At summary judgment, PACT argued only that its expert had shown Intel’s products actually process data. PACT did not argue that an apparatus claim can be infringed by a product that is merely capable of infringing. PACT raised that capability theory for the first time in a reconsideration motion, which the district court denied as untimely. The Federal Circuit agreed. Critically, PACT conceded at oral argument that if it had forfeited the capability argument, Intel was entitled to judgment on the ‘301 patent.

The ‘593 patent — prosecution estoppel narrows “dedicated connection.” During ex parte reexamination, PACT had argued to the Patent Office that a “dedicated connection” is “specifically devoted to connecting those two units, and thus not to other units.” The district court incorporated that concession into its claim construction, reading “physically dedicated connection” to require “a connection designed to directly interconnect a particular device to a particular memory via a link inaccessible to other devices and memories.” Under that construction, Intel’s accused processors — which use shared “CoreBo” and “CacheBo” interface modules with bus lines shared across multiple cores and memories — could not infringe. PACT argued that only “at least one segment” of a connection needed to be uniquely devoted, but the Federal Circuit found this broader reading flatly inconsistent with what PACT had told the Patent Office during reexamination.

Key Takeaways

• Capability arguments must be raised at summary judgment: A capability-based infringement theory for an apparatus claim — the device is capable of infringing even if not currently configured to infringe — must be argued when opposing the initial summary judgment motion, not first raised in a reconsideration motion.
• IPR and reexamination statements are potent estoppel weapons: Arguments made during inter partes review and ex parte reexamination to distinguish prior art routinely constrain claim scope in later district court litigation, just as statements in the original prosecution file history would.
• The “dedicated” modifier is taken seriously: Claiming a “physically dedicated connection” in a processor patent means exactly that — a link no other device can share. Shared bus architectures will not qualify, especially when the patentee said as much during reexamination.
• Cross-proceeding argument consistency matters: Patent holders who argue narrow claim scope at the Patent Office to survive validity challenges cannot later argue broader scope in court to establish infringement.

Why It Matters

This case is a textbook illustration of two traps that recurrently ensnare patent assertion entities. The first is the procedural forfeiture trap: fail to make the right argument at the right procedural moment, and you lose it permanently. PACT had a potentially viable theory — Intel’s processors are capable of processing data sequences, which under Federal Circuit precedent can suffice to infringe an apparatus claim — but it did not raise that theory at summary judgment. By the time PACT filed a reconsideration motion, it was too late.

The second trap is the prosecution estoppel trap: what you say to the Patent Office during examination, IPR, and reexamination will be used against you in litigation. PACT argued narrow claim scope during reexamination to confirm its patents, a move that preserved the claims — but then bound it to that narrow scope when trying to prove infringement. Intel’s shared memory architecture could not fit within the narrow construction PACT itself had endorsed. For patent litigators and licensing entities, the takeaway is clear: carefully audit all post-grant proceedings and prosecution history across a patent family before developing a claim construction and infringement strategy for district court.